Computer Engineering Seminar
Variations – and Aging Tolerant 6T SRAM Designs
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In this talk, first, the stability problem of Diffusion-Notch-Free (DNF) SRAM cells used in dense Last Level Caches (LLC) is presented. A DNF cell eliminates lithographic induced variations due to NMOS diffusion notches used in conventional 6T SRAM cells. However, it also results in reduced overall cell stability. A new WL Under-Drive (WLUD) circuit that enables a read stable DNF cell with all minimally sized devices (called M-cell) is proposed. Write stability is also maintained at low voltage with a VCC Dynamic Voltage Collapse (DVC) scheme that trades large dynamic cell retention margin for improving write stability. Another DNF cell, called P-cell, with PMOS pass device and charged high bit-lines is also presented. This cell is inherently read ratioed and extra read margin can be obtained through upsizing the NMOS PD without creating a notch as in conventional cell. A VSS DVC circuit is used along the P-cell to recover write stability. Second, the various problems of a passive clamping circuit to support 6T SRAM sleep mode is presented. Sleep mode minimizes leakage power consumption in SRAM arrays when they are not accessed. To provide appropriate sleep voltage without affecting memory states, a passive clamping circuit has been widely used. However, to generate reliable sleep voltage, the passive clamping circuit requires substantial design guardband for variations and aging. To minimize the guardband (thus maximize leakage power reduction), an active clamping technique is proposed.
Nam Sung Kim is an Assistant Professor at the University of Wisconsin–Madison. He was with Intel Corporation as a senior research scientist from 2004 to 2008 after he received his Ph.D. degree in Computer Science and Engineering from the University of Michigan–Ann Arbor in 2004. He has published more than 30 technical papers in refereed international conferences and journals and served in technical program committees of several prominent international conferences. He was a recipient of the award at the IEEE Design Automation Conference (DAC) Student Design Contest in 2001 and the best paper award at the IEEE International Conference on Microarchitecture (MICRO) in 2003. He was also a recipient of Intel Fellowship. His research interest is robust and low-power circuits, microarchitecture, and system design in nanoscale technology.