Towards General Purpose Specialization

Abstract

With slowing technology scaling, specialized accelerators are increasingly attractive solutions to continue expected generational scaling of performance. However, naive specialization limits accelerator applicability to narrow domains. This is problematic practically because algorithms are constantly evolving, and intellectually as codesign innovations are often siloed into their respective domains. I will discuss three potential directions to address this problem.

The first direction is to improve accelerator generality: we conceive of a “general purpose” accelerator ISA, stream-dataflow, which abstracts the typical behaviors of domain-specific accelerators. This includes decoupled memory/computation, coarse-grain control, spatially-local communication, and ISA control of data-reuse. Importantly, we explore how to expose “irregular” (ie. data-dependent) computation and memory access patterns; we find that joins and alias-free indirection are key idioms to support in an accelerator ISA. Our evaluation shows accelerators with these abstractions can achieve order-of-magnitude improvements over GPUs; however, many of their features are expensive and not useful for every workload. Therefore, a second direction is automated codesign: Our framework, DSAGEN, enables users to search for the best programmable architecture given a set of input C/C++ kernels, using principles of modular hardware and compilation. Finally, while accelerators typically have rich interfaces that enable taking advantage of high-level program behavior, general purpose processors still lack this capability. Our third direction explores adding rich semantic interfaces for memory access in general purpose ISAs.

Biography

Tony Nowatzki is an assistant professor of computer science at the University of California, Los Angeles, where he leads the PolyArch Research Group. He joined UCLA in 2017 after completing his PhD at the University of Wisconsin — Madison. Dr. Nowatzki’s research interests include computer architecture, microarchitecture, hardware specialization, and compiler codesign. His work has been recognized with an NSF CAREER grant, three IEEE Micro Top Picks awards, CACM Research Highlights, an IEEE Best of CAL award, and a PLDI Distinguished Paper Award.