Robust Computation with Subthreshold Leakage Currents

With diminishing VLSI process feature sizes, leakage currents have been increasing exponentially, to a point where leakage power and dynamic power in an IC are roughly equal.Traditional VLSI design approaches see this as a serious problem. However, we see this "problem" as an opportunity. Instead of viewing leakage currents as an attendant evil, we use them exclusively to perform computation. The benefits of doing this are:
* Power consumption is reduced by 100-500X
* Power-delay product is improved by 10-20X.
The downside to this approach are that circuit delays increase by 10-25X. However, this is not a problem for a wide class of portable, wearable and embedded computing applications. Another downside is that subthreshold currents have a strong dependence on process, voltage and junction temperature (PVT) variations.
Without addressing these 3 problems, subthreshold design cannot become a viable mainstream design approach. We have developed a rubust PVT variation tolerant subthreshold design approach employing dynamic body biasing techniques. Using this idea, we fabricated a 0.25um subthreshold design, and I will present post-fabrication results from this effort. I will conclude with a quick summary of the other research efforts that my group is working on.

Sunil Khatri received his BS. MS and PhD degrees from IIT Kanpur (India), UT Austin and UC Berkeley respectively. He spent 4 years at Motorola Inc., where he was part of the design teams for the MC88110 and PowerPC 603 design teams. He is currently an Assistant Professor at Texas A&M University. He has co-authored over 130 peer-reviewed technical papers, one book, one book chapter and
5 US patents. His research interests include VLSI circuit design (to address power, radiation tolerance, variation tolerance, and crosstalk),VLSI logic synthesis, and hardware acceleration of VLSI CAD algorithms using GPUs and FPGAs.