Niagara 2 and Paralleo Programing with Transactional Memory

I will give a quick overview of Niagara 2 which will motivate the rest of the talk. The key to achieving performance with CMPs is writing efficient and correct parallel programs. Unfortunately, this has proved almost impossible for the average software developer. Hardware based transactional memory, a research technology that brings the idea of database transactions to parallel programming, provides a potential solution to this problem. In this talk I will describe a variant of hardware transactional memory and the implications that using transactions as the main abstraction for parallelism has on optimizing the performance of parallel programs.

Kunle Olukotun is an Associate Professor of Electrical Engineering and Computer Science. Olukotun received his Ph.D. from The University of Michigan. Olukotun led the Stanford Hydra single-chip multiprocessor research project which pioneered the combination of chip multiprocessor (CMP) and thread-level speculation (TLS) technologies. Olukotun founded Afara Websystems to develop commercial server systems with CMP technology. Afara was acquired by Sun Microsystems; the Afara microprocessor, called Niagara 1, is at the core of Sun's "throughput Computing" initiative. Olukotun is actively involved in research in computer architecture, parallel programming environments and scalable parallel systems.