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Systems Seminar - CSE

Multiple Instruction Stream Processor

Richard Hankins
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Microprocessor design is undergoing a major paradigm shift towards multi-core designs. To support this trend, we propose the Multiple Instruction Stream Processing (MISP) architecture. MISP introduces the "sequencer" as a new category of architectural resource and defines a canonical set of instructions to support user-level inter-sequencer communication and control transfer. In essence, MISP allows an application program to directly manage user-level threads without OS intervention and without a radical shift in the multithreaded programming paradigm.

This presentation describes the design and evaluation of the MISP architecture for the IA-32 family of microprocessors, and introduces the audience to the MISP programming model. By using a research prototype MISP processor, we demonstrate the feasibility of implementing the MISP architecture and show that legacy multithreaded applications can easily be migrated to use MISP.
Richard Hankins is a member of Intel's Microarchitecture Research Lab, where he investigates architectural extensions to support the upcoming multi- and many-core architectures. Richard received his Ph.D. in Computer Science from the University of Michigan in 2004. As a member of Michigan's Database Group, Richard explored architecture-conscious database management systems.

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