Malleable Network Processors

Overhead of memory accesses limits the performance of packet processing applications. While the memory bottleneck has been a concern for much of computing, the memory-access-intensive nature of packet processing combined with the rapid growth in link-bandwidths aggravates the problem further. To address this, packet-processing systems can utilize a wide-array of mechanisms such as: multi-level memory hierarchies, wide-word accesses, special-purpose result-caches, data caches, asynchronous memory, and hardware multi-threading. This talk will consider two fundamental problems in building a packet processing platform that is both easy to program and is effective in addressing the memory bottleneck. First, what minimal set of mechanisms must a packet processing system should support in hardware? Second, how should one partition the available chip-space among these mechanisms so that the resulting platform achieves good performance in a wide-range of deployment scenarios? We show that no fixed partitioning is sufficient, and describe novel architecture for a malleable network processor.

The above research is a part of Project Shangri-La – the long-term objective of Shangri-La is to create a programming environment that will make future-generations of packet processing systems as easily programmable as today's servers and workstations. Development of such systems will facilitate creation of high-performance, network overlay hosting facilities, which can help address Internet ossification. In this talk, I will describe the overall vision the status of our research.

Finally, I will describe the vision and mission of Systems Research Lab – a new R&D initiative that I am starting at the Tata Research, Development and Design Center (TRDDC) in Pune, India. TRDDC is the R&D division of Tata Consultancy Services (TCS) – Asia's largest IT Company.
Harrick Vin is a Professor of Computer Sciences and the Director of the Advanced Systems Research Laboratory at the University of Texas at Austin. He is also the head of the Systems Research Lab (SRL) being started at the Tata Research, Development and Design Center (TRDDC) in Pune, India. TRDDC is the R&D division of Tata Consultancy Services (TCS) – Asia's largest IT Company.

Harrick's research interests are in the areas of networks, operating systems, distributed systems, and multimedia systems. Harrick received his Ph.D. in Computer Science from the University of California at San Diego in 1993. He has co-authored more than 100 papers in leading journals and conferences. Harrick is a recipient of several awards including the Faculty Fellow in Computer Sciences, Dean's Fellowship, National Science Foundation CAREER award, IBM Faculty Development Award, Fellow of the IBM Austin Center for Advanced Studies, AT&T Foundation Award, National Science Foundation Research Initiation Award, IBM Doctoral Fellowship, NCR Innovation Award, and San Diego Supercomputer Center Creative Computing Award. He has served on the Editorial Board of ACM/Springer Multimedia Systems Journal, IEEE Transactions on Multimedia, and IEEE Multimedia. He has been a guest editor for IEEE Network. He has served as the program chair, the program co-chair, and a program committee member for several conferences.