Design and Synthesis of Approximate Computing Circuits

As CMOS technology is scaled into the nanometer regime, power consumption has become one of the paramount concerns in designing VLSI circuits. At the same time, with the prevalence of mobile and embedded computing, there is an increasing demand for signal processing, multimedia, machine learning, and pattern recognition applications. One feature of these applications is that they can tolerate some error in the computation results. The relaxation of the accuracy requirement for these applications leads to a new design paradigm, known as approximate computing. It deliberately sacrifices a small amount of accuracy to achieve improvement in performance and power consumption. In this talk, I will first give some background on approximate computing. Then, I will present our research work in this area. The first topic is a novel high-accuracy approximate adder that significantly reduces the power-delay product compared to the accurate adders. It is suitable for many error-tolerant applications such as image processing and machine learning. The second topic is logic synthesis algorithms for approximate computing. I will cover several algorithms developed by our group for different design types, such as ASICs and FGPAs. These algorithms explore the design space and return a good design that satisfies the error specification.
Weikang Qian is an assistant professor in the University of Michigan-Shanghai Jiao Tong University Joint Institute at Shanghai Jiao Tong University. He received his Ph.D. degree in Electrical Engineering at the University of Minnesota in 2011 and his B.Eng. degree in Automation at Tsinghua University in 2006. His main research interests include electronic design automation and digital design for emerging technologies. His research was nominated for the Best Paper Awards at the 2009 International Conference on Computer-Aided Design (ICCAD) and the 2016 International Workshop on Logic and Synthesis (IWLS).