Computer Engineering Seminar
Challenges in the Evolution of Server-class Instruction-set Architectures
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Microelectronic technology has been a fundamental factor in server-class microprocessor performance throughout the years. Smaller transistors and larger chips have made possible the development of ever more complex and faster microprocessors, by exploiting techniques such as deeper pipelines, instruction- and data-level parallelism, thread-level parallelism, speculative execution, wide instruction words, and so on. However, such growth is facing serious challenges due to limits in power consumption and power density. While the search for solutions to the technology challenges is ongoing, there appears to be an opportunity for performance enhancement through evolution of the instruction-set architectures in server-class microprocessors. It is frequently possible to reduce computing demands through specialized functionality, as it has been demonstrated in areas such as signal processing, multimedia processing or network computing in the embedded systems space. Such enhancement style has not found widespread adoption in the server space, due to the legacy implications arising from changing the instruction-set architecture.
In this talk, we review our reasoning behind the need for evolution in instruction-set architectures for server-class systems, and the challenges found in pursuing such objectives. We summarize the need for identifying "what" new functionality is desirable, as well as the need to determine "how" the new functionality can be added to an instruction-set architecture and enabled for widespread utilization. This talk focuses on describing the challenges as opposed to proposing solutions; in doing so, the intention is to describe an area that has been somewhat neglected in recent years, and which appears ready for new research based on lessons learned in embedded systems.
Dr. Jaime H. Moreno is the Senior Manager of Computer Architecture, IBM Research Division (Yorktown Heights, NY). His department is involved in the architecture definition, concept phase and high-level design of IBM's microprocessors, including power-aware design and power/performance trade-offs in processor design, and compiler optimization for modern processor architectures. He joined IBM Research in 1992; following three years as a faculty member at the University of Concepcion (Chile). Jaime has performed research in various processor architectures, including VLIW, superscalar, embedded and digital signal processors. He is co-author of a research monograph, and a textbook on digital systems. He is a Master Inventor at IBM Research. Jaime holds M.S. and Ph.D. degrees in computer science from UCLA in 1985 and 1989, respectively, and obtained a degree in electrical engineering from the University of Concepcion (Chile, 1978).